Part Number:LMP91000
Hi. I'm making a prototype with which I'm going to sense Co2, C2H4 and O2 (the sensors are from alphasenser, 3 cells and 2 cells). At the moment I do not want to weld the PBC to the LMP91000 so I'm going to need a socket, my question is, which socket do you recommend for the lmp91000?
Part Number:OPA2140
I would like to know if there is any information about current consumption (assuming unloaded outputs) when OPA2140's inputs are beyond the normal operation range, especially closer to the positive range (i.e. above (V+)-3.5V). The data sheet have information about this part not having phase inversion when inputs are overloaded, which is good. However I would also like to know if the current consumption behavior is also predictable.
Many aaeons ago I used a part (C-MOS AFAIR) whose supply current increased significantly when inputs were beyond the linear Vcm range. I just want to make sure that is not the case with the OPAx140 as my application requires a good behavior under such circumstances.
Part Number:PGA112
I am intending to use the PGA112 amplifier to measure voltages with a wide dynamic range. Peak voltage to be measured is 60 V, scaled to < 3V with a 100k / 4.7k resistor divider, and low-passed as appropriate to the application. The output of the PGA112 will then go through an output filter to the 12-bit ADC of a Piccolo or Delfino uC.
Application details: This is for sensing phase voltage in a BLDC motor controller where the controller can both be used with a wide variety of bus voltages (Vbus = 6V - 60V), and where the phase voltage will vary at 0 - 500 Hz between 0 V and duty_cycle*Vbus for 0 < duty_cycle < 1.
The application will use the gain of the PGA to adjust for changes in Vbus; for example, when running at 6V a gain of 8 will be used. However, I am not intending to change gain dynamically (between sequential readings of voltage) if at all possible. Therefore, at a given gain, the question of usable dynamic range of the PGA/ADC combination arises. Essentially, the ADC has a nominal resolution of 3.3V / 2^12 = 0.8 mV/count, but the bottom 50 mV = 62 counts are indistinguishable. If my input varies from 0V to 100 mV (very reasonable for scaled phase voltages at low duty cycle), a full half of the output is clipped and indistinguishable.
QUESTION 1: Is there a different approach I should be taking here, either with the PGA112 or a different part, to solve this problem? I considered using no amplifier gain and instead a single-ended-to-differential amplifier and the 16-bit mode of the Piccolo/Delfino ADC, but for various reasons this is not ideal.
QUESTION 2: If I continue to use the PGA112, can I set Vref to 100 mV to offet the output? I understand that this would restrict me to gains of 2+ (as Vref has no impact with gain=1), and slightly restrict my output range (from 100 mV to DVdd - 50 mV). Are there other impacts I'm missing? The datasheet discusses Vref=GND and Vref=AVdd/2 cases, but not the general case.
QUESTION 3: What's the most appropriate way to get a Vref in this range, with the necessary current source/sink requirements? I expect to have a REF3230 available for Vcal; should I buffer this, resistor-divide by 30, and re-buffer? Is an OPA2364 appropriate for both buffering stages here? Is it acceptable to have the output of the second buffer (the 100 mV Vref) shared by 4x PGA112s? (Output current of OPA2364 = 45 mA >> 4x PGA112 Vref current = 4*2 mA.)
QUESTION 4: Is there a PSPICE / TINA-TI model of the PGA112 available so I can answer some of these questions on my own?
Part Number:THS4531
Hi,
Could you please provide a circuit recommendation for TMS320F28379D ADC signal conditioning, please refer to this thread for background: here.
Thanks!
Chuchen
Part Number:tlc2272a
I am using the TLC2272A opamp to detect peak current in a PWM-controlled LED driver.
Typical Operation:
In the schematic below, the PWM control signal is applied to the gate of Q1-A and LED current flows from the positive supply through the LED (connected to node TO_LED) through Q1-A and sense resistor R2 to ground. The circuit must detect LED current at levels as low as 0.3mA, which translates to 30mV across sense resistor R2. U1-A is a peak detector which rapidly charges C1 to 6X the highest level seen on sense resistor R2.
When LED current is removed, Voltage on R2 drops to 0, the output of op-amp U1 drops to 0, and C1 slowly discharges through R4 and the load at the ADC input (1KΩ in series with a 20pf sample and hold capacitor sampling at a 100KHz rate). Software interprets peak detector output below 50mV as an LED-off condition. Leakage in the ADC input is ±1nA - therefore, the ADC input is not supplying a small amount of leakage current to partially charge C1.
The Issue:
At room temperature, in some newly-assembled boards (pick-place/reflow from an assembly house), some peak detectors cannot bring their outputs below 50mV to get the expected “no LED current” indication. Often, a failure will be one or two per board (8 detectors per board) with two failures usually within one pack (these are dual op-amp packs). Usually, replacing the affected pack solves the problem.
Some failures are also seen when the circuit is operated at elevated temperature in an environmental chamber. As above, the failures may happen in pairs within the same IC pack.
Input offset voltage for the TLC2272A is 1.5mV
Any suggestions what may be causing the described problem?
Part Number:INA114
Tool/software:TINA-TI or Spice Models
Hi,
The input referred noise below 10kHz quoted for the INA114 IA is around 15nV/sqrt(Hz) for a gain of 80 according to the datasheet (p. 4 www.ti.com/lit/ds/symlink/ina114.pdf
But the simulation below shows over 29nV/sqrt(Hz), any idea why?
Thanks in advace
Part Number:MSP430F5419A
Hi,
I use TLV8801 for ADC input buffer. I found OPA output will generate a sin wave, but if I remove the resistance between OPA and ADC, this sin wave is gone.
OPA input is voltage divider. Ru=1MOhm, Rd=1MOhm.
If I pass OPA, connect voltage divider to ADC directly. Then I can get correct voltage!
I don't know why this result, pls help give me right answer.
Part Number:INA166
Need Help!
i am using IC INA 166 for hydrophone which has 10pf capacitance with frequency range 270kHz to 330kHz and input voltage level is 1uVpp.
what should i do for impedence matching so i can proccess aforementioned signal to be 1mVpp at low noise density.
Part Number:INA114
Planning to use INA114 for signal conditioning of a bridge circiut.
Unknown resistance varies from 0 to 1Kohms.
It will be read by ADS1258. Output of the Signal Conditioner has to swing 0 to 5V.
(Please refer the Picture
attached)
When the unknown resistance is zero, output of the signal conditioner has to be 5V. But it only gives out put of 2.01V.
The Required gain is 2.
Please help to resolve the issue.
Part Number:LMP7721
Hello everyone,
I'm working for my PhD prototype about high impedance sensors and I need to simulate and calculate some theorical values of them.
I'm looking for about different parameters about two operational amplifiers that I can't find:
1) Input resistance and input capacitance of the LMP7721
2) Differential resistance (between two inputs) of the LMP7721
3) Input resistance and input capacitance of the TLV333
4) Differential resistance (between two inputs) of the TLV333
These information is basic to study the small signal model circuit of the sensors that I am using, but It's not avaliable on datasheet and I don't know how I can obtain It or estimate.
Could someone help me?
Thanks to advance
Robert
Part Number:PGA308
Hello,
I'm troubleshooting a design using a PGA308. I have been able establish bidirectional communication but it appears that I'm not doing something correctly with the internal device setup.
For instance when attempting to set the output offset using either the course or fine offset registers the only outcome is that the offset moves either to V+ or GND.
Can you provide me with a set of register setup values based on my design?
Analog Connections:
Current RAM writes:
- Write SFTC Register – Command = 0x07, Data = 0x0050
- Write CFG2 Register – Command = 0x04, Data = 0x0C00
- Write ZDAC Register – Command = 0x00, Data = (fine offset unsigned 16 bit value)
- Write GDAC Register – Command = 0x01, Data = (fine gain unsigned 16 bit, 0.333=0x0000, 0.999=0xFFFF)
- Write CFG0 Register – Command = 0x02, Data = xxx1yyyyzzzzzzzz
Where: xxx = Final Gain Code (0x0=2, 0x1=2.4,…0x6=6)
yyyy=Front End Gain Code (0x0=4,…0xD=1600)
zzzzzzzz=Coarse Gain (2’s compliment, -63 to +63, 0x00=0, 0xff= -1, 0x80=-FS, 0x7f=+FS)
Scott
Hi
I am doing a noise-analysis on this amplifer. But it gives me a very low noise number, can anybody see whats wrong. I have attached the file. Thank you.(Please visit the site to view this file)
Part Number:INA117
Hi everyone,
What is the meaning “Rated Voltage” of parameter Output in INA117 datasheet p2.
Rated Voltage Io=+20mA, -5mA Min : 10V Max :12V
Does it correspond to Output swing according to a specific impedance ? I don’t think. Does it correspond to a maximum output voltage ?
Thank you for your help,
Best regards,
Mathieu
Part Number:INA333
Hi,
I am working through a setup trying to simulate noise in the INA333 using TINA. I have already gone through and calculated the results by hand but wanted to run a simulation for verification. I am not getting the expect output for the noise spectral density or Total noise graphs.
I did some searching online and found this presentation on the exact topic I was looking for. I worked through the results got a matching answer by hand but when trying to simulate I run into a number of issues.
My Circuit is the following image and I have included my TINA file.
Issues:
1) If I do not have R8 (100K) on Vout then TINA reports issue with U1.Q21 "Operating point not found".
This resistor was not there in the linked ppt presentation but was there in the INA333 Tina file downloaded from the web.
2) Once adding R8 the issue changes to U2.D17 "Operating point not found".
I then removed the OPA333 circuit setting the Vref CM to mid-supply and just used a voltage source.
3) Finally the Noise analysis will run but only if I set "Analysis>>Mode>>"Single". The TINA comments in blue specify to use "analysis>>Mode>>"Parameter Stepping" but will not run in this mode.
Once running in the "single mode" I get a different response from the presentation on slides 30 and 31.
An image of my Total noise graph looks as follows:
The graph for noise spectral density is also very different. I initially thought it had to do with Log scale on axis but once I changed the axis to match I still had different results.
To summarize: I would like to know if it looks like I am missing a step when trying to simulate noise in the ina333. I have an identical circuit to the one in the linked presentation but cannot repeat the results.
(Please visit the site to view this file)(Please visit the site to view this file)
Part Number:OPA3692
Hi,
In one of our new designs, we need to drive three loads from a single composite video ( 75 ohm, NTSC/ PAL) input.
I am planning to use OPA3692 buffer for this, by shorting its 3 inputs.
Please let me know whether this IC can be used for this kind of applications.
Thanks & Regards,
Madhu
Part Number:TLV07
Hi,
one of my customer is testing TLV07 to measure the DC bus current in their solar inverter system.
The schematic is as below, the shunt resistor is at the GND side, so the common mode voltage is almost zero. The current is DC, and there will be 20k ripple since an inverter of 20k switching frequency is connected to the DC BUS.
The layout is as below:
They test OP07 and TLV07 at the same circumstance with the same board, the test result is as below:
| POWER | current measured by OP07(A) | current measured by power analyzer(A) | error percentage(%) |
| 5% | 0.58 | 0.71 | -18.3 |
| 10% | 1.29 | 1.40 | -7.85 |
| 15% | 2.00 | 2.08 | -3.85 |
| 25% | 3.34 | 3.40 | -1.76 |
| 50% | 6.60 | 6.61 | -0.15 |
| 75% | 9.88 | 9.88 | 0 |
| 100% | 12.81 | 12.79 | 0.15 |
| POWER | current measured by TLV07(A) | current measured by power analyzer(A) | error percentage(%) |
| 5% | 0.47 | 0.68 | -30.88 |
| 10% | 1.07 | 1.38 | -22.46 |
| 15% | 1.79 | 2.06 | -13.11 |
| 25% | 3.19 | 3.39 | -5.9 |
| 50% | 6.71 | 6.71 | 0 |
| 75% | 10.30 | 10.09 | 2.08 |
| 100% | 12.83 | 12.44 | 3.14 |
Can anyone give me some suggestions how to improve the behavior or TLV07 to compete against OP07? Thanks.