Recently, I am debugging an ultrasonic receiving circuit as shown in Figure 1.
Due to the high impedance of the ultrasonic sensor, a JFET op-amp LF356 is used to convert the high impedance to low impedance and a second stage circuit is used to further amplify the signal.
Figure 1 Schematic for the ultrasonic receiving circuit
When testing the circuit, the receiving signal of the first stage output could be measured using an oscilloscope, but there exist a moving DC offset. The DC offset drops gradually from +3V to about -3V. For convenience, a video is recorded and could be watched from here. The output of the second stage is purely a DC offset(at about -4.1V) and the ultrasonic signal could not be noticed.
In order to exclude the soldering faults, a 200kHz signal from a signal generator (The center frequency of the sensor is at about 156kHz.) has been fed into the circuit. In this case, the output of the two stages both works well.
This problem has confused me for several days. It would be greatly appreciated if someone could give me some advice.